1. Field of the Invention
The present invention pertains to the packet technology known as Asynchronous Transfer Mode (ATM), and particularly to determining delay (in terms of frames) of time slots of a multiframe received on Plesiochronous Digital Hierarchy (PHD) transmission network.
2. Related Art and Other Considerations
The increasing interest for high band services such as multimedia applications, video on demand, video telephone, and teleconferencing has motivated development of the Broadband Integrated Service Digital Network (B-ISDN). A suitable technique to support B-ISDN is know as Asynchronous Transfer Mode (ATM), which offers considerable extension of telecommunications capabilities.
ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and traditionally have a fixed size. A traditional ATM cell comprises 53 octets, five of which form a header and forty eight of which constitute a xe2x80x9cpayloadxe2x80x9d or information portion of the cell. The header of the ATM cell includes a Header Error Control (HEC) byte, as well as two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual path is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
At its termination points, an ATM network is connected to terminal equipment, e.g., ATM network users. Typically between ATM network termination points there are plural switching nodes, the switching nodes having ports which are connected together by physical transmission paths or links. Thus, in traveling from an originating terminal equipment to a destination terminal equipment, ATM cells forming a message may travel through several switching nodes.
A switching node has a plurality of ports, each of which can be connected by via a link circuit and a link to another node. The link circuit performs packaging of the cells according to the particular protocol in use on the link. A cell incoming to a switching node may enter the switching node at a first port and exit from a second port via a link circuit onto a link connected to another node. Each link can carry cells for plural connections, a connection being e.g., a transmission between a calling subscriber or party and a called subscriber or party.
The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially functions like a cross-connect between ports of the switch. Paths internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a message ultimately to travel from an ingress side of the switch to an egress side of the switch, and ultimately from the originating terminal equipment to the destination terminal equipment.
Currently ATM transmission networks for lower speed applications are primarily based on Plesiochronous Digital Hierarchy (PHD) transmission networks (see ITU-T Recommendation G.702). A mapping for transport of ATM cells on the different PDH bit rates, e.g., for both 1544 and 2048 frame structures, has been provided (see ITU-T Recommendation G.804, ATM Cell Mapping Into Plesiochronous Digital Hierarchy (PHD) (November 1993). These frame structures are described in ITU-T Recommendation G.704, xe2x80x9cSynchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 734 kbit/s Hierarchical Levels (July 1995). Each frame of a multiframe has a series of time slots, the time slots having an octet structure.
The mapping of ATM cells into a frame as specified in ITU-T Recommendation G.804 subsumes certain basic principles for both 1.5 and 2 Mb/s PCM based ATM connections. These basic principles are as follows: (1) The ATM cells are mapped into all time slots in a consecutive order (each ATM cell covering several times slots); (2) the bytes in the ATM cell are aligned with the octet structure of the frames; (3) the cells have a 53 byte rate and are not aligned to the frame structure; (4) time slots 1-15 and 17-31 are used for ATM cells in the 2 Mb/s connection (time slot 16 not being used); (5) time slots 1-24 are used for ATM cells in the 1.5 Mb/s connection; (6) the forty eight bytes of ATM cell payload can be scrambled in order to protect against false delineation; (7) empty cells are transmitted as fillers. The empty cells can be of three types: an idle cell, an unassigned cell, and an IMA filler cell. An idle cell has a predetermined header of the following octet values (in hexadecimal as indicated by the suffix xe2x80x9cHxe2x80x9d): 00H, 00H, 00H, 01H, and 52H (the 52H being the Header Error Control (HEC) byte). The payload of the ATM idle cell has each of its forty eight octets having the value 6AH. An unassigned cell has a header with the following octet values: 00H, 00H, 00H, 00H, 55H. In Inverse Multiplexing for ATM (xe2x80x9cIMAxe2x80x9d), filler cells replace idle cells. The filler cell for IMA has the pattern 00H,00H,00H,0BH, and 64H.
Fractional mapping involves the use of only a portion of the time slots of a frame, e.g., from one to thirty time slots. Fractional mapping can be conceptualized as a screening mask, where each time slot can be either in a state xe2x80x9cusedxe2x80x9d or a state xe2x80x9cunusedxe2x80x9d. Fractional mapping in general is specified in ITU-T Recommendation G.704. Fractional mapping-for ATM per se is not specified in ITU-T Recommendation G.804, but the fractional mapping of ITU-T Recommendation G.704 can be applied to ATM.
Since the ATM cell length of 53 octets is a prime number, the headers of ATM cells will move periodically over all time slots (as long as the number of used time slots per frame is less than 53). When the number of used time slots is less than 53, the following characteristics will apply: (1) Each time slot will contain the start byte of an ATM cell exactly one time within a 53 frame interval; (2) Five consecutive time slots will have a complete ATM header within a 53 frame multiframe or period; (3) There will be a deterministic number of frames between the beginning of an ATM cell in time slot n and the beginning of an ATM cell in time slot n+1
As described below, there are envisioned technologies in which the time slots used for ATM transport may be delayed. What is needed therefore, and an object of the present invention, is a technique for aligning time slots to compensate for such delay.
A time slot aligner determines delay (in terms of frames) of time slots of frames received on Plesiochronous Digital Hierarchy (PHD) transmission network. In accordance with the time slot frame/delay determination technique of the invention, the time slot aligner finds an initial header of an ATM cell by searching five consecutive time slots in nearby frames. Once the initial header is found, a frame/delay value is determined for each time slot comprising the header. The frame/delay values for selected time slots of the header are then used to form a window which is used for searching for the next header. Searching for a next header for a next ATM cell involves sliding the window to other frames and searching for a value in a successive time slot which will form a HEC byte for a header framed by the sliding window. When a next header is located, a frame/delay determination has to be made only for the last time slot of the header, e.g., the time slot which formed the HEC byte. A new window is then formed using the frame/delay pattern from the most-recently acquired header, and that new window slid to find yet another header. Header location, time slot frame/delay determination, and formation of a new window continue until a frame/delay determination is made for all time slots.
Two modes of the time slot frame/delay determination technique are provided, particularly a Trial and HEC-Error mode and an Idle Cell Aligner mode. In the Idle Cell Aligner mode, once an initial header of an idle cell is located a known relationship is employed to determine which frame has the header of a next ATM cell beginning in a predetermined location, e.g., the second time slot of initial header. The predetermined relationship and the window of the initial header is used to locate all non-HEC bytes of the next header. Using the contents of non-HEC bytes of the next header, a HEC value is computed for that next header. The computed HEC value is then located in appropriate time slot, and the frame/delay therefor determined. Until frame/delay determinations are made for all time slots, the Idle Cell Aligner mode continues to look for a new header, to determine the frame/delay of the last time slot thereof (the HEC time slot), and to form a new window for use (in combination with the known relationship) for locating another header.